3.5 Inch UART Propono Exemplar: DMG48320F035_01W (COF Series) Featured Image

3.5 Inch UART Display
Exemplar: DMG48320F035_01W (COF Series)

DWIN 3.5inch-320*480 UART DISPLAY

Features:

● Ex T5L0, ratio currit DGUS II.

● 3.5 inch, 320*480 elementa resolutio, 262K colorum, IPS-TFT-LCD, angulum late visum.

● Smart LCD cum CTP/RTP/sine TP.

COF compages.Totum nucleum ambitus screen captiosus in FPC of LCM figitur, quod in structura levi ac tenui, parvo pretio et facili productione, figitur.

50 fibulae inclusae IO, UART, CAN, AD et PWM ab usuario CPU core facilioris progressionis secundae.

Mitte ad nos inscriptio Datasheet 3D Data

Specification

Descriptio

Product Tags

Video

Specification

ASIC Information

T5L0 ASIC

T5L0 ASIC vis humilis est, cost-efficax, GUI et applicatio valde integrata uno-corre dual-corio ASIC designata a DWIN Technologia pro parva magnitudine LCD et massa anno 2020 producta.

Ostendere

Color			262K colorum
LCD Type			IPS, TFT LCD
Viewing Anglus			Lata visens angelum, valorem typicum 85°/85°/85°/85°(L/R/U/D)
Propono Area（AA）			48.96mm (W) ×73.44mm (H)
Resolution			320×480
Backlight			LED
splendor			DMG48320F035_01WTC:300nit DMG48320F035_01WTCZ01:300nit DMG48320F035_01WTCZ02:50nit DMG48320F035_01WTR:300nit DMG48320F035_01WN:350nit

Voltage & Current

Potentia Voltage			3.6~5.5V
Operatio Current			165mA VCC=5V, max backlight
			70mA VCC=5V, backlight off

Reliability Test

Operatio Temperature			-10℃~60℃
Repono Temperature			-20℃~70℃
opus Umor			10%~ 90% RH, valorem typicum 60% RH

Interface

User interface			50Pin_0.5mm FPC
Baud rate			3150~3225600bps
Output intentione			Output 1:3.0~3.3 V
			Output 0, 0~0.3 V
Input intentione RXD）			Input 1；3.3V
			Input 0；0~0.5V
Interface			UART2: TTL; UART4: TTL, （ tantum available post OS configuratione UART5: TTL, （ tantum available post OS configuratione
Data Forma			UART2: N81; UART4: N81/E81/O81/N82;4 modi (OS configuration) UART5: N81/E81/O81/N82;4 modi (OS configuration)

Interface

Pin	Definition	I/O*	Eget Description
1	5V	I	Virtutis copia, DC3.6-5.5V
2	5V	I	Virtutis copia, DC3.6-5.5V
3	GND	GND	GND
4	GND	GND
5	GND	GND
6	AD7	I	5 input ADCs.12-bit resolutio in casu 3.3V potestatis copia.0-3.3V input intentione.Exceptis AD6, reliqua notitia ad Core OS per UART3 mittitur tempore reali cum 16KHz sampling rate.AD1 & AD5 parallelis adhiberi possunt, & adhiberi possunt AD3 & AD7 parallelis, quae sunt duobus 32KHz sampling AD.AD1, AD3, AD5, AD7 in parallelis adhiberi possunt, quae aequantur ipsi 64KHz sampling AD;notitia summatur 1024 temporibus et deinde divisa per 64 ut obtineat 64Hz 16bit AD valorem per oversampling.
7	AD6	I
8	AD5	I
9	AD3	I
10	AD2	I
11	3.3	O	3.3V output, maximum pondus 150mA.
12	SPK	O	EXTERNUS MOSFET ad stridorem vel oratorem repellere.Resistor externus 10K ad terram detrahi debet ut potestas in gradu inferiori sit.
13	SD_CD	I/O*	SD/SDHC interfacies, SD_CK capacitorem 22pF cum GND prope SD card interface coniungit.
14	SD_CK	O
15	SD_D3	I/O*
16	SD_D2	I/O*
17	SD_D1	I/O*
18	SD_D0	I/O*
19	PWM0	O	II 16 bis PWM output.Resistor externus 10K ad terram detrahi debet ut potestas in gradu inferiori sit. Core OS in tempore reali per UART3 regi potest
20	PWM1	O
21	P3.3	I/O*	Si utens RX8130 vel SD2058 I2C RTC ad utrumque IOs, SCL coniungi debet P3.2, & SDA cum P3.3 in parallelis connecti cum 10K resistenti viverra usque ad 3.3V.
22	P3.2	I/O*
23	P3.1/EX1	I/O*	Adhiberi potest ut externum 1 input simul interrumpat, et sustinet utrumque planum intentione humili vel ore trahens modos interrumpendos.
24	P3.0/EX0	I/O*	Adhiberi potest ut externum 0 input simul interrumpere, sustinet utrumque gradum intentionis humilis vel ore trahens modos interpellandi.
25	P2.7	I/O*	IO interface
26	P2.6	I/O*	IO interface
27	P2.5	I/O*	IO interface
28	P2.4	I/O*	IO interface
29	P2.3	I/O*	IO interface
30	P2.2	I/O*	IO interface
31	P2.1	I/O*	IO interface
32	P2.0	I/O*	IO interface
33	P1.7	I/O*	IO interface
34	P1.6	I/O*	IO interface
35	P1.5	I/O*	IO interface
36	P1.4	I/O*	IO interface
37	P1.3	I/O*	IO interface
38	P1.2	I/O*	IO interface
39	P1.1	I/O*	IO interface
40	P1.0	I/O*	IO interface
41	UART4_TXD	O	UART4
42	UART4_RXD	I	UART4
43	UART5_TXD	O	UART5
44	UART5_RXD	I	UART5
45	P0.0	I/O*	IO interface
46	P0.1	I/O*	IO interface
47	CAN_TX	O	Can interface
48	CAN_RX	I	Can interface
49	UART2_TXD	O	UART2 (UART0 Vide portum OS core)
50	UART2_RXD	I	UART2 (UART0 Vide portum OS core)